1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, more particularly to a method of manufacturing a semiconductor device whose parasitic capacitance between wiring is small, and to a semiconductor device.
2. Description of the Related Art
Of the prior art methods of forming wiring of a semiconductor device, there is a well-known technique for processing trench wiring. According to this technique, a trench having a wiring pattern in an interlayer insulating film is formed and the trench is filled with conductive materials, such as a metal and the like. In such a technique for processing the trench wiring, an etching stopper film is used so that the to-be-formed trenches have the same depths uniformly. In general, as the etching stopper film, a silicon nitride film as an insulating film is used (U.S. Pat. No. 4,789,648).
FIGS. 7A to 7F are diagrams each showing a manufacturing step of a semiconductor device by applying the technique for processing trench wiring using the etching stopper film.
First, a first interlayer insulating film 203 is formed on a semiconductor substrate 201 with a surface area on which first wiring 202 is formed as shown in FIG. 7A. A silicon nitride film as an etching stopper film 204 is formed on the first interlayer insulating film 203 as shown in FIG. 7B. A predetermined area of the etching stopper film 204 is etched. More particularly, only a portion which corresponds to a formation area of a via hole (which will be described later) is selectively etched so as to be removed. An opening part 205 is formed in the etching stopper film 204 (FIG. 7C). Next, a second interlayer insulating film 206 is formed on the first interlayer insulating film 203 and the etching stopper film 204 (FIG. 7D). A wiring trench 207 for forming wiring is formed in a formation area of second wiring by etching the second interlayer insulating film 206. Because the etching stopper film 204 exists, only the second interlayer insulating film 206 is etched. A via hole 208 is formed in the first interlayer insulating film 203 by using the etching stopper film 204 as an etching mask (FIG. 7E). Then, metal materials are laid in the wiring trench 207 and the via hole 208 for forming second wiring 209 so as to complete the semiconductor device (FIG. 7F).
According to such a technique explained above, the etching stopper film 204 is formed above the whole surface of the semiconductor substrate 201 excluding the via hole 208. The etching stopper film 204 necessarily exists between the first wiring 202 and the second wiring 209. In other words, in the abovedescribed manufacturing method, the etching stopper film 204 intervenes between the second wiring 209 and adjacent second wiring 209 (not shown). The etching stopper film 204 is formed of silicon nitride (including silicon oxide nitride).
The silicon nitride film has a higher degree of permittivity than a silicon oxide film which is generally used as an interlayer insulating film. Thus, parasitic capacitances between a piece of wiring and another wiring formed on the same layer, and between pieces of wiring formed on different layers are large. Accordingly, a problem arises that the parasitic capacitance becomes remarkable in size, as the structure of the wiring is complicated. As the parasitic capacitance becomes large in size, reliability of operation of the semiconductor device decreases.